1. Field of Invention
The present invention relates generally to the field of pipeline analog-to-digital converters. More specifically, the present invention relates to the calibration of pipeline analog-to-digital converters for improved performance.
2. Discussion of Prior Art
Pipeline A/D converters provide a high resolution and high throughput without the exponential scaling of flash converters. Each stage within the pipeline samples an analog input value, produces a k-bit decision, adjusts and multiplies the input value to produce a residue to the following stage. The complete Analog-to-Digital Converter (ADC) word appears at the output once the input sample has propagated through all of the stages in the pipeline. Typically, a pipeline converter operates in two phases; a sampling phase, and a multiply phase. During the sampling phase an analog input value is stored and a k-bit decision is produced. During the multiply phase, a stage outputs an adjusted analog sample, called a residue, to the following stage that conversely will be in the sampling phase. A conventional pipeline ADC is shown in FIG. 1. The input voltage is sampled by the first stage during phase one (Φ1). During phase two (Φ2) the input just sampled is multiplied and adjusted by a multiple of the reference voltage (VREF) to produce a residue. The following stage samples the residue, generated by first stage, during Φ2 and performs the multiplication and subtraction during Φ1. Each stage in the pipeline processes the residue presented by the previous stage generating k-bits until the input sample has propagated through all of the stages in the pipeline. Bits generated by each stage in the pipeline are captured, shifted and aligned by simple digital latches producing a digital output word. The maximum error must be less than a least significant bit (LSB) for linear operation.
Within each stage, capacitor mismatch causes the gain to vary from the ideal desired multiple. These mismatches can result in missing codes or missing decision levels. Circuit performance is also affected by the amplifiers finite open-loop gain. The limited gain of the amplifier causes the output not to reach its final value. The effects of capacitor mismatch and amplifier gain, in the simple 1-bit per stage case, can be estimated by the following expression:
  Vo  =            Vi      ·                        C          1                          C          2                    ·                        1          +                                    C              1                        /                          C              2                                                1          +                                    1              +                                                C                  1                                /                                  C                  2                                                      A                                +                  Vref        ·                              (                          -              1                        )                                b            i                              ⁢              1                  1          +                                    1              +                                                C                  1                                /                                  C                  2                                                      A                              In addition to capacitor mismatch and insufficient amplifier open-loop gain, errors can also be introduced by switch charge injection, comparator offset and amplifier offset. However, circuit and clocking techniques have been developed to compensate for these errors.
Calibration of pipeline A/D converters have been addressed in the prior art before. They fall into two categories: foreground calibration and background calibration. Foreground calibration methods require the converter to halt operation during the calibration period. Background calibration methods can operate while the converter continues to sample.
Circuit techniques also exist for handling these errors. A reference refreshing technique presented in the paper to Shih et al. entitled, “Reference Refreshing Cyclic Analog-to-Digital and Digital-to-Analog Converters,” compensates for the loop gain in a cyclic A/D converter. A capacitor charge transfer technique as described in the paper to Li et al. entitled, “A Ratio Independent Algorithmic Analog-to-Digital Conversion Technique,” compensates for capacitor mismatch in a cyclic A/D converter. A double correlated sampling technique as presented in the paper to Li et al. entitled, “A 1.8V 67 mW 10b 100MS/s pipelined ADC using Time-Shifted CDS technique,” corrects finite amplifier open-loop gain with minimal overhead in a pipeline A/D converter. These methods use additional cycles to perform their correction. Another method as presented in the paper to Yu et al. entitled, “A 2.5V, 12-b, 5MS/s Pipelined CMOS ADC”, commutates the capacitors to minimize the DNL.
To maintain optimum performance in pipeline analog-to-digital converters, calibration methods have been developed that correct for errors introduced by capacitor mismatch and limited amplifier open-loop gain. The calibration method presented in the paper to Karanicolas et al. entitled “A 15-b, 1-MS/s Digitally Self-Calibrated Pipelined ADC,” uses a 1.93 radix per stage to eliminate missing decision level errors and is digitally calibrated off-line. This is a foreground calibration technique; and this circuit requires an amplifier with sufficient open-loop gain, because the amplifier gain can vary during normal operation due to thermal conditions. The one-time calibration compensates well for capacitor mismatch but will not track variations during normal operation.
The calibration method described in the paper to Moon et al. entitled, “Background Digital Calibration Techniques for Pipelined ADC's,” uses a background calibration technique called skip-and-fill. This technique inserts a calibration voltage into the pipeline without halting the normal flow. However, this requires a reconstruction filter to recover the missing data; the reconstruction filter is a nonlinear interpolator and will introduce bandwidth limitations. However, such prior art calibration techniques fail to teach continuous calibration of pipelined ADCs without loss of data.
The technique described in the paper to Ingino et al. entitled, “A Continuously Calibrated 12-b, 10MS/s, 3.3-V A/D Converter,” is capable of continuously operating while performing a background calibration. However, the stage being calibrated is taken offline resulting in a non-optimum calibration. Also, the additional switches make this method impractical for a large number of stages.
The technique as described in the paper to Fu et al. entitled, “A Digital Background Calibration Technique for Time-Interleaved Analog-to-Digital Converters,” uses time-interleaving to switch between completely separate converters. Fu's method requires a complete duplication of ADC's to perform calibration on pipelines that are currently not in use.
The method described in the paper to Murmann et al. entitled, “A 12-bit 75-MS/s Pipelined ADC Using Open-Loop Residue Amplification,” implements correction using statistical data gathering to correct the output data.
The prior art methods described above are limited in their scope and effectiveness. The foreground technique cannot function while the converter is sampling and, therefore, does not track the continuously changing operating conditions. The background techniques available today use complex non-ideal digital reconstruction, a great deal of overhead, or deficient calibration. Hence, the prior art solutions fail to teach a background calibration circuit that allows optimal background calibration of pipeline A/D converters. Furthermore, prior art solutions fail to teach a circuit that continuously compensates for capacitor mismatch and provides finite amplifier gain with minimal complexity and without the loss of any samples.
Whatever the precise merits, features, and advantages of the above cited references, none of them achieves or fulfills the purposes of the present invention.